1. Field of the Invention
The present invention generally relates to an analog multiplying circuit and a variable gain amplifying circuit. More specifically, the present invention is directed to an analog multiplying circuit for multiplying two analog signals with each other in a modulating/demodulating circuit of a wireless appliance so as to perform a frequency conversion of the multiplied analog signal, and also to a variable gain amplifying circuit.
2. Description of the Related Art
Very recently, a large number of circuits for processing high frequency (radio frequency) signals are used in wireless appliances, in particular, a great number of such circuits as amplifiers and frequency converters are employed in these wireless appliances. On the other hand, power supply voltages applied in order to operate these circuits are gradually lowered. For instance, in general, the power supply voltage Vcc was selected to be 4.8 V a several years ago. In current wireless appliances, generally speaking, the power supply voltage Vcc is selected to be 2.6 V.
FIG. 9 is a circuit diagram of the conventional dual balanced type analog multiplying circuit (Gilbert cell mixer) constituted by bipolar transistors. In this analog multiplying circuit, first analog differential signals V1p and V1n are applied to both a common base of transistors Q2 and Q3 and a common base of transistors Q1 and Q4 of two sets of differential pairs Q1xe2x88x92Q2 and Q3xe2x88x92Q4 which employ the transistors Q1 through Q4. A collector of the transistor Q1 is connected to a collector of the transistor Q3 so as to form an output terminal Vop, and a collector of the transistor Q2 is connected to a collector of the transistor Q4 so as to form an output terminal Von. Also, these collectors are connected via load resistors R1 and R2 to a power supply voltage Vcc. To an emitter of the differential pair Q1xe2x88x92Q2 and an emitter of the differential pair Q3xe2x88x92Q4, collectors of transistors Q5 and Q6 are connected, respectively. Second analog differential signals V2p and V2n are applied to bases of the transistors Q5 and Q6. An emitter of the transistor Q5 and an emitter of the transistor Q6 are connected to a collector of a transistor Q7 and a collector of a transistor Q8, which constitute a current source of a current value Ics, respectively. A feedback resistor Re capable of linearizing a second analog signal input unit is connected between the emitter of the transistor Q5 and the emitter of the transistor Q6. A bias voltage Vb is applied to both a base of a transistor Q7 and a base of a transistor Q8.
Assuming now that a voltage of a base-to-emitter of the transistor Q5 is equal to Vbe5, and a voltage of a base-to-emitter of the transistor Q6 is equal to Vbe6, both an output current I3 of the transistor Q5 and an output current I4 of the transistor Q6, which constitute a first differential amplifier, may be expressed by the following formulae (1) and (2):
I3=Ics+(V2pxe2x88x92V2nxe2x88x92Vbe5+Vbe6)/Rexe2x80x83xe2x80x83(1)
I4=Icsxe2x88x92(V2pxe2x88x92V2nxe2x88x92Vbe5+Vbe6)/Rexe2x80x83xe2x80x83(2)
As a result, an output current 2*xcex94I=I3xe2x88x92I4 is represented by the following formula (3):                                                                         2                *                Δ                ⁢                                  xe2x80x83                                ⁢                I                            =                              I3                -                I4                                                                                        =                              2                *                                                      (                                          V2p                      -                      V2n                      -                      Vbe5                      +                      Vbe6                                        )                                    /                  Re                                                                                                        =                              2                *                                                      {                                          V2p                      -                      V2n                      +                                              Vt                        *                                                  ln                          ⁡                                                      (                                                          I4                              /                              I3                                                        )                                                                                                                }                                    /                  Re                                                                                        (        3        )            
Note that the voltages between the bases and the emitters of the transistors Q5 and Q6 are assumed as:
Vbe5=Vt*ln(I3/Is),
xe2x80x83Vbe6=Vt*ln(I4/Is)
Also, assuming now that a current flowing through the load resistor R1 is I1, a current flowing through the load resistor R2 is I2, and symbol Vt is a thermal voltage, a differential output I1xe2x88x92I2 may be expressed by the below-mentioned formula(4) if the base current is neglected:                                                                         I1                -                I2                            =                              xe2x80x83                            ⁢                              2                *                Δ                ⁢                                  xe2x80x83                                ⁢                I                *                tan                ⁢                                  xe2x80x83                                ⁢                h                ⁢                                  {                                                                                    (                                                  V1p                          -                          V1n                                                )                                            /                      2                                        ⁢                    Vt                                                                                                                          =                              xe2x80x83                            ⁢                              2                *                                                      {                                          V2p                      -                      V2n                      +                                              Vt                        *                                                  ln                          ⁡                                                      (                                                          I4                              /                              I3                                                        )                                                                                                                }                                    /                                                                                                                        xe2x80x83                            ⁢                              Re                *                tan                ⁢                                  xe2x80x83                                ⁢                h                ⁢                                  {                                                                                    (                                                  V1p                          -                          V1n                                                )                                            /                      2                                        ⁢                    Vt                                    }                                                                                        (        4        )            
Furthermore, when V1pxe2x88x92V1n less than  less than Vt, the below-mentioned formula can be approximatively satisfied:
tan h{(V1pxe2x88x92V1n)/2Vt}=(V1pxe2x88x92V1n)/2Vt.
Then, as expressed in the following formula (5), two signals are multiplied with each other:
I1xe2x88x92I2=2*{(V2pxe2x88x92V2n)+Vt*In(I4/I3)}/Re*{(V1pxe2x88x92V1n)/2Vt}xe2x80x83xe2x80x83(5)
In the conventional circuit shown in FIG. 6, a total number of longitudinally-stacked stages of the transistors is selected to be 3 stages. As a consequence, a minimum power supply voltage Vcc(min) required in such a case that silicon bipolar transistors are used must be higher than, or equal to 2.6 V in order that both the voltages between the bases and the emitters of the transistors, and also the amplitude voltages of the input/output signals can be secured, as the power supply voltage Vcc(min).
However, since the conventional analog multiplying circuit cannot be operated under such a power supply voltage lower than, or equal to 2.6 V, this conventional analog multiplying circuit owns the problem that this analog multiplying circuit cannot be used in the presently available wireless appliances having the power supply voltage of 2.6 V.
The present invention has been made to solve the above-explained problem, and therefore, has an object to provide such an analog multiplying circuit operable in a highly linear mode under low power supply voltage lower than, or equal to 2.6 V.
To solve the above-explained problem, an analog multiplying circuit, according to the present invention, is featured by such an analog multiplying circuit comprising: a first differential pair constructed of a first transistor and a second transistor, the emitters of which are commonly connected to each other; a second differential pair constructed of a third transistor and a fourth transistor, the emitters of which are commonly connected to each other; a first input terminal connected to a commonly-connected base of the second transistor and the third transistor; a second input terminal connected to a commonly-connected base of the first transistor and the fourth transistor; a first output terminal connected to a commonly-connected collector of the first transistor and the third transistor; a second output terminal connected to a commonly-connected collector of the second transistor and the fourth transistor; a first resistor connected between the first output terminal and a power supply; a second resistor connected between the output terminal and the power supply; a fifth transistor, the collector of which is connected to the commonly-connected emitter of the first differential pair; a sixth transistor, the collector of which is connected to the commonly-connected emitter of the second differential pair; a third resistor connected between an emitter of the fifth transistor and the ground; a fourth resistor connected between an emitter of the sixth transistor and the ground; first input means connected to a base of the fifth transistor; and second input means connected to a base of the sixth transistor; wherein: the first input means is arranged by first current generating means, first current mirror means constituted by both the fifth transistor and a seventh transistor, a fifth resistor connected between an emitter of the seventh transistor and the ground, and a third input terminal connected to the emitter of the seventh transistor; and the second input means is arranged by second current generating means, second current mirror means constituted by both the sixth transistor and an eighth transistor, a sixth resistor connected between an emitter of the eighth transistor and the ground; and a fourth input terminal connected to the emitter of the eighth transistor. Since such a circuit arrangement is employed, the analog multiplying circuit can be operated under low power supply voltages.